1. Field of the Invention
The present invention generally relates to a chip package structure, and in particular, to a stacked-type chip package structure and a fabrication method thereof.
2. Description of Related Art
A stacked-type chip package structure is a semiconductor package structure in which a three-dimensional package technology is employed to vertically stack a plurality of chips. The stacked-type chip package structure can be applied to storage devices such as memory modules, memory cards, portable flash disks, and so forth. The memory module normally applying to a desktop computer, a notebook computer, or an industrial computer is a standardized product, such as a dynamic random access memory (DRAM) module. To satisfy computing requirements of the computers, the storage capacity and the access speed of the memory module have been continuously advanced. According to the prior art, a plurality of memory chips of a conventional single in-line memory module or a conventional dual in-line memory module is disposed on a single circuit board. By way of a surface mount technology (SMT), each pin of the memory chips is soldered to the circuit board. In addition, through an insert type surface bonding interface (e.g. a gold-finger connector) disposed on the circuit board, the memory module is inserted into a PCI bus slot on a motherboard of the computer for transmitting required information.
Nevertheless, due to a rising demand for the storage capacity of the memory module, the number of the memory chips increases accordingly, and additional area occupied by the circuit board is required. Based on the above, the memory module with a three-dimensional package structure will prevail over the conventional memory module whose storage capacity is not able to be rapidly and significantly expanded.
Most common package technologies applied to the memory module include a wire bonding technology, a flip-chip bonding technology, a package on package technology, a gold to gold interconnection (GGI) technology, a through silicon via (TSV) technology, and so on. All of the aforesaid package technologies adapted to the three-dimensional package structures are developed for meeting the requirement for the storage capacity of high-density memories.
The TSV is elaborated herein as an example. First, vias having a high aspect ratio are fabricated on a silicon substrate. A conductive material is then filled into the vias, and solder balls are formed on the silicon substrate. Thereby, the solder balls are electrically connected to the conductive material filled in the vias. Referring to FIG. 1 illustrating a stacked-type chip package structure, a plurality of chips 10 is sequentially stacked, and every two adjacent chips 10 are separated by an adhesion layer 40. A plurality of solder balls 30 is disposed between every two adjacent chips 10 and electrically connected to a conductive material 20 in vias 12 defined in and extending through each of the chips 10. Thereby, the chips 10 are electrically conducted to each other. After that, a sealant 50 can be filled between the chips 10, so as to protect the solder balls 30.
Nevertheless, fabricating the vias having a high aspect ratio on the silicon substrate is not cost-effective, and is inferior to mass production. Besides, when an arrangement of the solder balls 30 on the chips 10 follows the trend of fine pitch, the shortened distance between the solder balls 30 may give rise to an overflow of the solder balls 30 during a reflow process, which is likely to cause circuit shortage. Moreover, the fabrication of the vias having a high aspect ratio on the silicon substrate negatively affects electrical performance and reliability of integrated circuits in the chips, thus poses an impact on the operation of the entire circuit system.